1. Field of the Invention
This invention relates to the manufacture of semiconductor devices having at least two layers of overlapping topologies formed during device manufacture, such as EPROMs, EEPROMs and the like and, more specifically, to reduction of filament formation adjacent to the sides of underlying layers thereof.
2. Brief Description of the Prior Art
In the manufacture of semiconductor devices having plural layers of polycrystalline silicon (polysilicon) therein, a problem of polysilicon filament formation has existed wherein filaments of polysilicon are formed during the steps where lines formed of the second polysilicon layer (poly 2) and which cross underlying polysilicon lines (poly 1) are etched. In the prior art formation of an EPROM or EEPROM device, an interlevel dielectric is deposited on top of a deposited poly 1 layer. The interlevel dielectric and the poly 1 layer are then etched together to form the underlying poly 1 structures. During this said interlevel dielectric and poly 1 etch, the sides of the poly 1 layer topologies are exposed, whereby subsequent deglazes and oxidations act upon this poly 1 sidewall as will be explained hereinbelow. The first gate oxide is wet etched, producing an undercut under the poly 1 lines. next the gate oxide for periphery devices is grown, producing a thick oxide on the top corners of the poly 1 layer and then the second layer of polysilicon (poly 2) is deposited and etched. There are three processes within this flow or series of processing steps which form filaments. First, poly 1 filaments are formed because a thermal oxide is grown on the poly 1 side walls. This forms a thicker oxide on the top corners of the poly 1 which will hide a filament when the poly 1 is later etched, as for example, during the stacked gate etch of an EPROM or EEPROM transistor. Second, the undercut of poly 1 formed during the deglaze will hide a poly 2 filament when the poly 2 is later etched, as, for example, during the stacked gate etch of an EPROM or EEPROM transistor or during the poly 2 etch of MOS transistors, as in DRAMs, SRAMS, logic circuits, etc. Third, since the vertical thickness of poly 2 is much greater adjacent to steps over underlying topography, such as a poly 1 line, a filament will be formed if an anisotropic poly 2 etch is used, as, for example, during the poly 2 etch of VLSI circuits, where small geometries are required and one can not use an isotropic etch.
In the prior art, either an isotropic poly 2 etch is used or a filament cutting mask is used to eliminate the filament. The isotropic polysilicon etch has the disadvantage of requiring more relaxed design rules and therefor can not be used on VLSI circuits where high density is an issue. The filament cutting mask has the disadvantage of requiring an extra mask which has a critical alignment to the underlying layers and adding more processing steps. It is therefore readily apparent that a method of producing devices of the type described hereinabove is desirable wherein both poly 1 and poly 2 filaments are removed or not formed initially and which do not require the use of an isotropic polysilicon etch or a filament mask.